1. Field of the Invention
The present invention relates to memory devices, more particularly, to a parallel bit testing device and method for detecting defective memory cells within memory devices.
2. Description of the Related Art
A typical memory device includes a memory cell array, where each memory cell in the array may store data. To determine which memory cells, if any, are defective, a tester may perform a parallel bit test on the memory cell array. To perform the parallel bit test, the memory device is configured into a parallel bit test mode responsive to a test mode setting command from the tester. The tester writes test pattern data to the memory cell array, where each memory cell is paired with another memory cell and written with the same data. When a read command is provided from the tester, the memory device reads the data from the memory cell array, and compares the data read from each memory cell pair for congruency. The tester determines which pairs include a defective cell responsive to the comparison and replaces those defective pairs with replacement cells. Typically the defective pairs are replaced as units, e.g., the tester replaces a group of four memory cells containing the defective cell with four replacement cells. When both memory cells in a memory cell pair are defective, however, the comparison result may indicate that the memory cells are not defective, and thus the memory device fails to replace the defective memory cells.
In another type of parallel bit test, disclosed in Korean Patent Laid-Open Publication No. 2001-0037848, a memory device stores test pattern data in a test pattern register and compares the test pattern data read from memory cell array with the stored test pattern data to determine which memory cells, if any, are defective. Accordingly, the memory device is able to correctly detect defective memory cells, including the case where both memory cells in a memory cell pair are defective.
To ensure accuracy in the detection of defective memory cells, the parallel bit test is typically performed at least twice on the memory cell array, using the test data pattern and an inverted version of the test data pattern. Accordingly, the memory device and parallel bit test disclosed above requires the sequential storing of inverted and non-inverted test pattern data into the test pattern data register, which complicates and slows testing, and lowers productivity of the memory device. And in some parallel bit testing schemes, some of the memory cells within the array may store the test pattern data while other memory cells may store the inverted test pattern data, thus requiring the test pattern data register to store an increasing number of inverted and non-inverted test patterns.